1. Field
Exemplary embodiments of the present invention relate generally to semiconductor technology, and more particularly to a semiconductor apparatus and an operating method thereof to improve performance of a memory device having different set and reset times.
2. Description of the Related Art
FIG. 1 is a graph describing a phase change of a memory cell in a Phase Change Random Access Memory (PCRAM).
The graph illustrates the power required for a set and a reset operation as a function of time for a memory cell of a PCRAM. A set operation changes the memory cell from a reset, high resistance state (reset state) to a set, low resistance state (set state) while a reset operation changes the memory cell from a set state to a reset state.
As illustrated in FIG. 1, a set operation may require about eight times more time than a reset operation.
Generally, in a memory device, data may be written in units of a predetermined number of memory cells. Hence, during a write operation, a set operation may be performed on some of the memory cells at the same time as a reset operation is performed on other cells.
Thus, the time required for a write operation of a conventional memory device such as a PCRAM is dictated by the time required for the set operations to the memory cells, which may slow down the operation of a PCRAM.
The same problem occurs in any other memory device in which the time required for a write operation changes significantly according to the bit value to be written to a memory cell.